1. Field of the Disclosure
The present disclosure generally relates to synchronous circuits and, more particularly, to a system and method to generate and terminate clock shift modes during initialization of a synchronous circuit.
2. Brief Description of Related Art
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
In SDRAMs or other semiconductor memory devices, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. Delay-locked loops (DLLs) are synchronous circuits used in SDRAMs to synchronize an external clock (e.g., the system clock serving a microprocessor) and an internal clock (e.g., the clock used internally within the SDRAM to perform data read/write operations on various memory cells) with each other. Typically, a DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal (e.g., the system clock) is advanced or delayed until its rising edge is coincident (or “locked”) with the rising edge of a second clock signal (e.g., the memory internal clock).
FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins 14 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 14 may constitute memory address pins or address bus 17, data pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17-19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address strobe (RAS) signal, a column address strobe (CAS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 20. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 20 generally arranged in rows and columns to store data in rows and columns. Each memory cell 20 may store a bit of data. A row decode circuit 22 and a column decode circuit 24 may select the rows and columns in the memory cells 20 in response to decoding an address, provided on the address bus 17. Data to/from the memory cells 20 is then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) unit 26. The I/O unit 26 may include a number of data output buffers to receive the data bits from the memory cells 20 and provide those data bits or data signals to the corresponding data lines in the data bus 18. The I/O unit 26 may further include a clock synchronization unit or delay locked loop (DLL) 28 to synchronize the external system clock (e.g., the clock used by the memory controller (not shown) to clock address, data and control signals between the memory chip 12 and the controller) with the internal clock used by the memory 12 to perform data write/read operations on the memory cells 20.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock signal, a Chip Select signal, a Row Access Strobe signal, a Column Access Strobe signal, a Write Enable signal, etc. The memory chip 12 communicates to other devices connected thereto via the pins 14 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
FIG. 2 depicts a simplified block diagram of the delay-locked loop (DLL) 28 shown in FIG. 1. The DLL 28 receives a reference clock (ClkREF) 30 as an input and generates an output clock or the ClkOut signal 32 at its output. A ClkOut signal 32 is, in turn, fed back as a feedback clock (ClkFB) 34 as discussed later. The reference clock 30 is interchangeably referred to herein as “ClkREF”, “ClkREF signal”, “Ref clock signal” or “Ref clock”; whereas the feedback clock 34 is interchangeably referred to herein as “ClkFB”, “ClkFB signal”, “FB clock signal” or “FB clock.” The reference clock 30 is typically the external system clock serving the microprocessor or a delayed/buffered version of it. In the embodiment of FIG. 2, the system clock 36 is shown buffered through a clock buffer 37. The output of the clock buffer 37—i.e., the Ref clock 30—thus is a buffered version of the system clock 36. In a register controlled DLL, the Ref clock 30 is input into a bank of registers and delay lines 38 as shown in FIG. 2. The registers in the bank 38 control delay lines with phase difference information received from a phase detector 40, as discussed below. For the ease of discussion, the bank of registers and delay lines 38 in FIG. 2 is referred to as “the delay line block” hereinbelow.
The clock output of the delay line block 38—the ClkOut signal 32—is used to provide the internal clock (not shown) used by the SDRAM 12 to perform data read/write operations on memory cells 20 and to transfer the data out of the SDRAM to the data requesting device (e.g., a microprocessor (not shown)). Thus, as shown in FIG. 2, the ClkOut 32 is sent to a clock distribution network or clock tree circuit 42 whose output 43 may be coupled to SDRAM clock driver and data output stages (not shown) in the I/O unit 26 to clock the data retrieval and transfer operations. As can be seen from FIG. 2, the ClkOut signal 32 (and, hence, the FB clock 34) is generated using delay lines in the delay line block 38, which introduces a specific delay into the input Ref clock 30 to obtain the “lock” condition.
As noted before, the purpose of the DLL 28 is to align or lock the memory's 12 internal clock (not shown) to the system's external clock (e.g., the system clock 36). A phase detector (PD) 40 compares the relative timing of the edges of the system clock 36 and the memory's internal clock (not shown) by comparing the relative timing of their respective representative signals—the Ref clock 30 which relates to the system clock 36, and the FB clock signal 34 which relates to the memory's internal clock—so as to establish the lock condition. As shown in FIG. 2, an I/O delay model circuit 44 may be a part of the DLL 28 to function as a buffer or dummy delay circuit for the ClkOut signal 32 before the ClkOut signal 32 is fed into the phase detector 40 as the FB clock 34. It is noted that although the ClkOut signal 32 is shown as an input to the I/O delay model 44, in some practical applications, the ClkOut signal 32 may still be an input to the clock distribution network 42, but another clock signal (not shown) received from the clock distribution network 42 may be fed as an input to the I/O delay model 44 instead of the ClkOut signal 32. In any event, the output of the I/O model 44 (i.e., the FB clock 34) effectively represents the memory's internal clock, which may be provided through the clock driver and data output stages (not shown) in the I/O unit 26. The I/O delay model 44 replicates the intrinsic delay of the clock feedback path, which includes the delay “A” of the system clock input buffer 37 and delay “B” that includes the delay encountered by the ClkOut signal 32 in the output data path Thus, the I/O model 44 may be a replica of the system clock receiver circuit (not shown) that includes the external clock buffer 37, and the clock and data output path (not shown) so as to match respective delays imparted by these stages to the system clock 36 and the ClkOut signal 32, thereby making the Ref clock 30 and the FB clock 34 resemble, respectively, the system clock 36 and the internal clock (not shown) of the memory as closely as possible. Thus, the I/O delay model 44 attempts to maintain the phase relationship between the Ref clock 30 and the FB clock 34 as close as possible to the phase relationship that exists between the system clock 36 and the memory's internal clock (not shown).
The Ref clock 30 and the FB clock 34 are fed as inputs into the phase detector 40 for phase comparison. The output of the PD 40—a shift left (SL)/shift right (SR) signal 45—controls the amount of delay imparted to the ClkREF 30 by the delay line block 38. The SL/SR signal 45 may determine whether the Ref clock 30 should be shifted left (SL) or shifted right (SR) through the appropriate delay units in the delay line block 38 so as to match the phases of the Ref clock 30 and the FB clock 34 to establish the lock condition. The SL/SR signal 45 may be supplied to the delay line block 38 via a delay control unit 46, which may control the timing of application of the SL/SR signal 45 by generating a delay adjustment signal 47, which, in effect, serves the same purpose as the SL/SR signal 45 but its application to the delay line block 38 is controlled by the delay control unit 46. The delay imparted to the Ref clock 30 by the delay line block 38 operates to adjust the time difference between the output clock (i.e., the FB clock 34) and the input Ref clock 30 until they are aligned. The phase detector 40 generates the shift left and shift right signals depending on the detected phase difference or timing difference between the Ref clock 30 and the FB clock 34, as is known in the art.
FIG. 3 illustrates a timing mismatch between ClkREF 30 and ClkFB 34 operated on by the phase detector 40 in FIG. 2. As is seen from FIG. 3, ClkFB 34 is generated after an intrinsic delay (i.e., the total of delays A and B in FIG. 2) of tID seconds has elapsed since the receipt of the first rising edge of ClkREF 30 by the phase detector 40. The mismatch between the timing of ClkREF 30 and ClkFB 34 is corrected by the phase detector 40 by instructing the delay line block 38 with appropriate shift left (SL) or shift right (SR) indication 45 to provide a delay equal to m*tD, where “m” is the number of delay elements or delay lines in the delay line block 38 (m=0, 1, 2, 3, . . . ) and “tD” is the delay provided by a single delay element or delay line. For example, if the clock period (tCK) of the Ref clock 30 is 12 ns and tID=10 ns, then the DLL 28 has to push out the rising edge of ClkFB 34 or left shift ClkREF 30 by 2 ns (tCK−tID=2 ns) to establish a “lock” (i.e., the rising edges of the Ref clock 30 and the FB clock 34 are substantially “aligned” or “synchronized” or almost “in phase”). In this example, if tD=200 ps, then m=10. As is known in the art, the clock periods of ClkREF 30 and ClkFB 34 remain equal, but there may be a phase difference or timing mismatch (“lag” or “lead”) between the two clocks that is detected by the phase detector 40 and adjusted by the delay line block 38 using the SL/SR signal 45 from the phase detector 40.
FIG. 4 depicts through a block diagram the major circuit elements of the phase detector 40 in FIG. 2. The phase detector 40 may include two phase detection units: a coarse phase detector 50 and a fine phase detector 52. The outputs 53-54 of the coarse and fine phase detectors, respectively, are supplied to the delay control unit 46 as respective SL/SR signals. Thus, in the embodiment of FIG. 4, the SL/SR signal 45 of FIG. 2 may consist of two separate SL/SR signals, each from one of the corresponding coarse and fine phase detectors 50, 52. The coarse phase detector 50 may initially act on ClkREF 30 and ClkFB 34 to instruct the delay line block 38 to provide a coarse delay to CLkREF 30 to establish a coarse phase alignment between ClkREF 30 and ClkFB 34. Thereafter, the fine phase detector 52 may take over and perform “fine tuning” or fine phase alignment of these two clocks to establish a perfect lock condition. During operation of the coarse phase detector 50, the delay control unit 46 may ignore any output 54 from the fine phase detector 52 until the output 53 of the coarse phase detector 50 indicates a primary “lock” (albeit, a rudimentary or less than perfect lock) between ClkREF 30 and ClkFB 34. Then the delay control unit 46 receives the output 54 from the fine phase detector 52 to instruct the delay line block 38 to provide a fine delay to CLkREF 30 until a perfect or fine lock between CLkREF 30 and ClkFB 34 is achieved.
FIG. 5 shows an exemplary block diagram depicting various circuit elements constituting the coarse phase detector 50 depicted in FIG. 4. The coarse phase detector 50 includes a coarse phase detection (PD) window 56 that provides an initial delay of “tPDW” to ClkFB 34 to generate a delayed feedback clock signal (ClkFB2d) 57 at its output. The amount of the delay tPDW may be fixed or predetermined. Another delay element 58 provides tPDW/2 delay (i.e., half of the delay provided by the coarse PD window 56) to ClkREF 30 to generate a delayed reference clock signal (ClkREFd) 59 at its output. The ClkREFd signal 59 clocks the sampler circuits (here, in the form of a set of D flipflops) 60, 62 to sample the feedback clock (ClkFB) 34 and the delayed feedback clock (ClkFB2d) 57 as shown in FIG. 5. The outputs PH1 (64) and PH2 (65) of D flipflops 62 and 60, respectively, represent the value of their respective D inputs (CLkFB 34 or ClkFB2d 57) sampled at the rising edge of ClkREFd 59. The values of PH1 and PH2 at any given instant determine the phase of ClkFB 34 with respect to the phase of ClkREF 30 (i.e., whether ClkFB 34 is in phase, 180° out of phase, etc. with respect to ClkREF 30 as discussed below). The relation between the phases of PH1 64 and PH2 65 may determine, as discussed in more detail below, whether to shift the reference clock 30 to the left or to the right. A majority filter 66 may be provided to receive PH1 (64), PH2 (65), and a counting clock signal (not shown) as inputs, and to responsively generate an appropriate SL/SR signal as the output 53 of the coarse phase detector 50. Although the construction of the majority filter 66 is not shown here, it is known in the art that the majority filter 66 may include a binary up/down counter (clocked by a counting clock signal (not shown)), which is incremented or decremented by the values of PH1 and PH2 signals 64-65. The counting clock may be the same as the system clock 36 or the reference clock 30. However, it is noted that a certain number of counting of input clock pulses (i.e., clock pulses of the counting clock signal (not shown)) may be required by the counter in the majority filter 66 before an SL or SR signal can be output. For example, the majority filter 66 may always count up to four input clock cycles (c=4) before generating an SL or SR indication. Such counting may consume time and delay the shifting of the Ref clock 30 and, hence, may delay the establishment of the lock as discussed in detail later hereinbelow.
FIG. 6 illustrates a phase relationship between the PH1 (64) and PH2 (65) signals generated by the coarse phase detector 50 in FIG. 5. As is shown in FIG. 6, the relationship between the phases of PH1 and PH2 may be used to identify what is the phase of ClkFB 34 with respect to ClkREF 30. In FIG. 6, the term “DP” (difference in phase) denotes the relative phase of ClkFB 34 with reference to ClkREF 30. Thus, for example, when both PH1 and PH2 achieve “high” or logic “1” values after their respective rising edges, that may indicate that ClkFB 34 is more than 180° but less than 360° out of phase with respect to ClkREF 30 as shown in FIG. 6. When this phase relationship between ClkFB 34 and ClkREF 30 is in effect, a shift left (SL) signal may be generated by the coarse phase detector 50 (as illustrated in FIG. 7A). Similarly, shift right (SR) signal may be generated when appropriate phase relationship between PH1 and PH2 as depicted in FIG. 6 arises. The output 53 of the coarse phase detector 50 may indicate a phase equal condition (PHEQ) when a certain phase relationship between PH1 and PH2 exists as shown in FIG. 6. The PHEQ condition may signify that ClkFB 34 is either substantially in phase (˜0° phase difference) or substantially 360° out of phase with respect to ClkREF 30. Other phase relationships between ClkFB 34 and ClkREF 30 and corresponding function symbols in FIG. 6 are self explanatory and, hence, are not further discussed here.
FIGS. 7A-7C show the timing relationships among various waveforms in the coarse phase detector 50 of FIG. 5 and also shows whether the reference clock should be shifted left or right to establish a lock. In FIG. 7A, the coarse phase detector 50 is in the shift left (SL) mode because ClkFB 34 has more than 180° (but less than 360°) phase distortion (180<DP<360) with respect to ClkREF 30, thereby generating high (or logic “1”) values for both PH1 (64) and PH2 (65) signals. During the SL mode, the DLL 28 increases delay applied to ClkREF 30. FIG. 7B shows exemplary signal waveforms for PHEQ mode. As is shown in FIG. 7B (and also in FIG. 6), in the PHEQ mode, the value of PH1 is “high” or logic “1” whereas the value of PH2 is “low” or logic “0.” These values are generated when the phase of ClkFB 34 is similar (˜0° or ˜360° phase difference) to the phase of CLkREF 30. When the coarse phase detector 50 enters the PHEQ mode, the delay control unit 46 may start receiving output 54 from the fine phase detector 52. Thus, during PHEQ mode, fine phase detector 52 is active and after several successive PHEQ modes, a stable lock between ClkREF 30 and ClkFB 34 is established. FIG. 7C, on the other hand, shows the shift right (SR) mode of the coarse phase detector 50 because the phase distortion between ClkFB 34 and ClkREF 30 is more than 0° but less than 180° (0<DP<180), thereby generating a “low” or logic “0” value for both PH1 and PH2 signals as shown. During the SR mode, the DLL 28 decreases delay applied to CLkREF 30. Although the waveforms for the 180° phase distortion case (represented by the function symbol “P180” in FIG. 6) are not shown in FIGS. 7A-7C, it is noted here that when the phase of ClkFB 34 is around 180° out of phase with ClkREF 30, the coarse phase detector 50 enters the SL mode as depicted in FIG. 6.
FIG. 8 depicts a simplified and exemplary illustration of registers and delay lines in the delay line block 38 and also shows how the reference clock 30 is shifted through the delay lines during initialization of the DLL 28. FIG. 8 illustrates sixty-one (61) register-controlled delay lines in the delay line block 38. It is noted that the number of registers and delay lines in FIG. 8 are for illustration only. To make the function of DLL 28 simple, it is assumed that register #0 (R0) is on or active upon initialization of the DLL 28. This means that the reference clock 30 initially bypasses the delay lines in the block 38. In the example discussed hereinbefore with reference to FIG. 3, it was noted that if tCK=12 ns, tID=10 ns, and tD=200 ps, then the DLL 28 would need m=10, i.e., DLL 28 would add delays through ten delay lines. Thus, in this example, ten left shifts (SLs) would be applied to ClkREF 30 from the initial entry point (R0) and register #10 (R10) will represent the lock point. It was noted before that a left shift adds a delay whereas a right shift reduces a delay.
It is observed that during initialization of DLL 28, the SR (shift right) mode is not allowed, even though the DLL 28 could be in the SR region (e.g., the timing relationship between various clock waveforms may be similar to that in FIG. 7C) because there is no register on the right side of register #0 (R0) in FIG. 8.
FIG. 9 illustrates an exemplary set of waveforms for the reference clock 30 and the feedback clock 34 upon initialization of the DLL 28 in FIG. 1. The waveforms in FIG. 9 depict a situation where a forced left shift (ForceSL or Force Shift Left) of the reference clock 30 is performed, even though the DLL 28 may be in the shift right (SR) mode (indicated by the crossed out portion in FIG. 9). For example, for the waveforms in FIG. 9, if tCK=8 ns, tID=10 ns and tD=200 ps, then DLL 28 would need 6 ns of additional (forced left shift) delays to establish a lock upon initialization of the DLL 28 because, in FIG. 9, 6 ns=2tCK−tID=m*tD. With the foregoing values, the value of “m” (i.e., the number of delay lines or delay elements) needed to establish a lock is m=30. Such a relatively high value of “m” may extend the time needed to establish a lock, especially when the majority filter 66 is used during DLL initialization as is discussed below with the example in FIG. 10. It is noted that the ForceSL mode is exited once the PH1 signal goes “high” or assumes a logic “1” value.
FIG. 10 shows another exemplary set of waveforms for the reference clock 30 and the feedback clock 34 upon initialization of the DLL 28 in FIG. 1. For the timing relationship illustrated in FIG. 10, the DLL 28 would be in the shift right (SR) mode upon initialization. However, as discussed with reference to FIG. 9, the DLL 28 would be forced to enter the shift left mode (ForceSL mode) during initialization. For the waveforms in FIG. 10, if tCK=9.8 ns, tID=10 ns, and tD=200 ps, then the DLL 28 has to shift left by 9.6 ns (m*tD) using the ForceSL mode because 9.6 ns=2*tCK−tID=m*tD. With the foregoing values, the value of “m” (i.e., the number of delay lines or delay elements) needed to establish a lock is m=48. Therefore, if DLL 28 uses the majority filter 66 (with counting interval c=4, as mentioned before by way of an example with reference to FIG. 5) to establish lock during initialization, then 192 clock cycles may be needed to establish the lock point because c*m=4*48=192 tCK. Hence, the use of majority filter 66 during initialization may significantly slow down the lock point establishment. This example illustrates the need to reduce the time needed to establish a lock.
To reduce the lock time upon initialization of the DLL 28, the “On1x” mode may be enabled during initialization. Typically, the On1x mode is only enabled during the initialization. Further, during the On1x mode, the DLL 28 enables the shift left (SL) command on every clock cycle (of the reference clock 30), and the majority filter 66 remains disabled during the On1x mode. Thus, during initialization, the DLL 28 may not only enter into the ForceSL mode, but may also enter into the On1x mode to perform left shifting on every clock cycle to expedite lock point establishment. The On1x mode is typically exited when the DLL 28 enters the PHEQ mode. However, it is observed that the On1x mode is generally good for slow frequency clocks only (with large tCK), i.e., the ratio (tCK/tID)>0.5. A high frequency reference clock 30 (small tCK) may cause overshooting between the ClkREF 30 and ClkFB 34 after the On1x mode is exited by the PHEQ signal (which is generated when the DLL 28 enters the PHEQ mode as shown in FIG. 12).
FIG. 11 depicts an exemplary set of waveforms for a high frequency reference clock 30 and the corresponding feedback clock 34 upon initialization of the DLL 28 in FIG. 1. In the timing diagram of FIG. 11, tCK=3 ns, tID=10 ns, and tD=200 ps. Therefore, m*tD=4*tCK−tID=2 ns. Thus, m=10. However, as discussed below with reference to the expanded waveforms in FIG. 12, the overshooting between ClkREF 30 and ClkFB 34 occurs because On1x mode does not exit when m=10 is reached (i.e., when ten cycles of consecutive left shifts are performed), but exits when the DLL 28 enters the PHEQ mode. The overshooting results in this case because of small tCK (of ClkREF 30) and long feedback time (tFB) as discussed with reference to FIG. 12.
FIG. 12 shows an exemplary set of waveforms to illustrate the overshooting problem encountered upon the exit of the On1x mode at high clock frequencies. It is noted here that because of a large number of waveforms in FIG. 12, no reference numerals are provided in FIG. 12 for ease of discussion and illustration. It is seen from FIG. 12 that the DLL 28 enters the ForceSL and On1x modes upon initialization. Thus, the left shifting of ClkREF 30 starts immediately after the first clock cycle of ClkFB 34 is received as indicated by the set of SL clocks at the top in FIG. 12. The On1x mode shifts ClkREF 30 left on each clock cycle of ClkREf 30 as indicated by the counting of the SL clocks in FIG. 12. Further, during On1x mode, the majority filter 66 remains disabled as seen from the waveform of the “Majority Filter Enable” signal at the bottom of FIG. 12. The generation of phase relation signals PH1 and PH2 is also illustrated in FIG. 12. The PHEQ signal in FIG. 12 is generated when the relation between the PH1 and PH2 signals indicate the PHEQ mode (as illustrated in FIG. 6). The other remaining signals—i.e., the ClkFB2d and ClkREFd signals—are the same as those illustrated in FIG. 5.
In the timing diagram of FIG. 12, as in FIG. 11, tCK=3 ns, tID=10 ns, and tD=200 ps. Therefore, m*tD=4*tCK−tID=2 ns. Thus, m=10. Hence, it is seen from the ClkREF and ClkFB waveforms in FIG. 12 that these two clocks are aligned after ten (10) consecutive left shifts or delays. However, because of the intrinsic delay (tID), small tCK (high reference clock frequency), and a long feedback time or feedback delay (tFB=tID+m*tD=4*tCK in FIG. 12), the On1x mode adds four additional left shifts (as shown by clock numbered 11 through 14 in the SL signal in FIG. 12) by the time the On1x mode exits by the rising edge of the PHEQ signal. This results in the overshooting illustrated in FIG. 12, which not only disrupts the phase alignment between ClkREF and ClkFB, but also further slows the lock establishment time by adding extra delays to establish lock. Furthermore, after On1x mode exits, the majority filter 66 (which was disabled during the On1x mode) may be needed to establish the lock because ClkREF and ClkFB are still not aligned at the time of On1x mode exit. The use of the majority filter 66 may further add locking delays as discussed hereinbefore with reference to FIG. 10.
It was noted before that the ForceSL mode exits at the rising edge of PH1 signal (as shown in FIG. 12). However, as discussed in the preceding paragraph, if the On1x mode is continued after ForceSL mode ends (as shown in FIG. 12), the problem of overshooting on the feedback path may occur, especially when tFB>1*tCK (tFB=4tCK for the waveforms in FIG. 12), which is quite common in modern high speed system and reference clocks. Therefore, it may be desirable to disable the On1x mode prior to activation of the PHEQ signal so as to prevent the overshooting.
FIGS. 13A and 13B illustrate two exemplary circuits 70, 72, respectively, to generate and terminate ForceSL 74 and On1x 76 signals shown in FIG. 12. In the circuit 70 of FIG. 13A, the initialization pulse 75 (Init #) is active “low”. During initialization of DLL 28, the Init # signal goes low (preferably in a pulse form) to generate the ForceSL signal 74 (shown in FIG. 12) to enter the force shift left mode. The On1x signal 76 (shown in FIG. 12) is also generated similarly in the circuit 72 of FIG. 13B. The ForceSL mode is exited (i.e., the ForceSL signal 74 in FIG. 13B goes low) using the circuit 70 of FIG. 13A when the PH1 signal 64 goes high (as illustrated in FIG. 12). Similarly, the On1x mode is exited (i.e., the On1x signal 76 in FIG. 13B goes low) when the PHEQ signal 77 in the circuit 72 of FIG. 13B goes high (as illustrated in FIG. 12). It is seen from FIGS. 13A-B (and also from FIGS. 6 and 12) that the PHEQ signal 77 is generated when PH1 is high (logic “1”) and PH2 is low (logic “0”).
FIG. 14 depicts a set of waveforms illustrating the wrong ForceSL exit problem due to clock jitter. As in FIG. 12, because of a large number of waveforms in FIG. 14, no reference numerals are provided in FIG. 14 for ease of discussion and illustration. It was shown and discussed with reference to FIGS. 13A-B (and also with reference to FIG. 12) that ForceSL mode is exited when PH1 signal goes high. However, at long tCK (slower clock frequencies) and short tID, the clock jitter may cause the ForceSL mode to exit prematurely as shown through the waveforms in FIG. 14. In the embodiment of FIG. 14, the On1x mode is also exited together with the ForceSL mode. However, as discussed before with reference to FIG. 12, when the On1x mode is exited after the ForceSL mode, the problem of overshooting in the feedback path may occur, especially at higher frequencies. In case of the waveforms in FIG. 14, the untimely or wrong ForceSL/On1x exit results in activation of the majority filter 66 (through the Majority Filter Enable signal) to establish the lock. The majority filter 66, as already discussed before, significantly delays lock establishment, especially during DLL initialization. It is observed here that the wrong ForceSL exit problem may be solved using an appropriate filter, but the On1x overshooting problem may still remain.
Therefore, it is desirable to disable the On1x mode prior to activation of the PHEQ signal so as to prevent the overshooting on the feedback path, especially when the On1x mode is exited after the ForceSL mode. In the event that the ForceSL and the On1x mode are exited together, it may still be desirable to prevent wrong ForceSL exit due to clock jitter or noise without using additional filter circuits. It is also desirable to avoid wrong ForceSL exit and On1x overshooting problems so as to achieve faster DLL locking time.